A. Field of the Invention
This invention relates to sense amplifiers and, more particularly, to differential sense amplifiers used in conjunction with memory circuits.
B. Description of the Prior Art
In memory circuits, the memory cells are commonly organized into rows and columns. Wordlines are generally associated with rows of memory cells and bitlines are generally associated with columns of memory cells. These memory circuits are commonly implemented using complementary pairs Of bitlines as input/output ports to the memory cells. During a typical memory access, the appropriate wordline for a particular row of memory is selected and the complementary bitlines connected to a corresponding column of memory are used to access a specific memory cell. The complementary bitlines are also connected to a sense amplifier which differentially senses small signals in the bitlines to determine the then existing logic state contained within the memory cell. The sense amplifier then generates an amplified signal representing the sensed logic state to the next stage in the memory circuit.
One prior art sense amplifier traditionally used in memory circuits is the current mirror sense amplifier 121 as shown in FIG. 1. Use of sense amplifier 121 has been popular because of its static behavior, relative simplicity, and small size. However, with the increasing speed and density of memories, wide power supply ranges, and high power supply noise, conditions for prior art sense amplifiers 121 have become increasingly demanding.
The bitlines 113 and 115 used in conjunction with prior art sense amplifier 121 of FIG. 1 are designed to operate with a nominal start voltage of V.sub.CC -V.sub.TN. A problem associated with sense amplifier 121 is that it exhibits a propagation delay dependence on common mode voltage levels in bitlines 113 and 115 when the start voltages in these bitlines rise above the nominal start voltage and approach V.sub.CC. Causes for the rises in bitline voltages include power supply noise and subthreshold currents in the bitlines. The abnormally high bitline start voltages result in increased propagation delays at the output of prior sense amplifier 121 because of the increased time required for intermediate sense amp output 119 to settle. This propagation delay is commonly referred to as high bitline level delay push-out and is a well-known phenomenon. Memory circuits begin to exhibit functional failures as push-delay times increase. Thus, minimized push-out delays resulting from high bitline start voltages are strongly desired.
Traditional solutions designers use to address the push-out problem include adding dedicated circuitry to reduce noise as well as adding circuitry to limit subthreshold currents that precharge the bitlines. These solutions have not been successful because of only limited effectiveness or high design cost in regard to time, power, area, or performance. As a result, existing memory circuits must often be designed to handle the extra time necessary to accommodate delay associated with high bitline level delay push-out.